1. Field of the Invention
The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having a power decoupling capacitor formed in a peripheral circuit region.
2. Description of the Related Art
As semiconductor memory devices, such as dynamic random access memory (DRAM), become more highly integrated, it is necessary for them to meet the demand for high operational speed as well as large storage capacity. In addition, the required number of operation circuits increases in proportion to the level of integration of the semiconductor memory devices, which causes severe fluctuation noise in the power supply voltage (VDD) and ground voltage (VSS) during read/write operations. To solve this problem, a power decoupling capacitor is formed in the semiconductor memory device to filter noise existing in an operating voltage, such as the power supply voltage (VDD) and the ground voltage (VSS).
Many attempts have been made to form a decoupling capacitor of high capacitance in a peripheral circuit region by using the same structure of a capacitor formed in a memory cell array region. Specifically, one proposed technology calls for simultaneously forming the cell capacitor and the decoupling capacitor by using a capacitor over bit line (COB) type storage node in which the capacitor is formed over a bit line in the memory cell array.
FIG. 1 is a sectional view of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device 100 includes a cell array region A, in which a cell capacitor 102 is formed, and a peripheral circuit region B, in which a decoupling capacitor 104 is formed. A storage electrode 135a of the cell capacitor 102 and a storage electrode 135b of the decoupling capacitor 104 are formed on buffer layers 131a and 131b, respectively. The buffer layers 131a and 131b electrically connect the storage electrode 135a and 135b to buried contacts 130a and 130b, respectively. In the cell array region A, the storage electrode 135a is electrically connected to the buried contact 130a through the buffer layer 131a, while having a predetermined align margin.
The buried contact 130a is formed in the cell array region A after an interlayer dielectric layer 127 is patterned into a predetermined configuration so as to form a contact hole (not shown). The storage node electrodes 135a and 135b are formed on mold oxide layers 132a and 132b in the cell array region A and the peripheral circuit region B, respectively. In addition, the buried contact 130a of the cell array region A is electrically connected to an active region of a semiconductor substrate 105 through a gate electrode 120a and a self-align contact pad 125 which is self-aligned by space walls 122. More specifically, the buried contact 130a is electrically connected to source/drain regions (not shown) formed in the active region of the substrate 105, which are defined by an isolation region 110. A top surface of the gate electrode 120a is covered with a capping layer 124a, and a gate insulating layer 106a is formed below the gate electrode 120a. 
In the peripheral circuit region B, the buried contact 130b is formed directly on the capping layer 124b. Furthermore, a gate insulating layer 106b, a gate electrode 120b, the capping layer 124b and the buried contact 130b are stacked over the semiconductor substrate in sequence. Meanwhile, the buffer layer 131b, which is formed on the buried contact 130b, is used as a connection line for connecting a plurality of decoupling capacitors 104 in series. Moreover, a plate electrode 137 of the decoupling capacitor 104 is connected to a metal interconnection 140 through a metal contact 139.
FIG. 2 is an equivalent circuit diagram of the decoupling capacitors formed in the peripheral circuit region of the conventional semiconductor memory device illustrated in FIG. 1. However, in more recent developments, the buffer layer 131a has been omitted in the cell array region A. Accordingly, a predetermined scheme in which the buffer layer 131b is omitted and the decoupling capacitor 104 is directly connected to the buried contact 130b in the peripheral circuit region B has been proposed. This scheme is illustrated in FIG. 3, where FIG. 3 is a sectional view of another conventional semiconductor memory device.
In comparison with the conventional memory device 100 of FIG. 1, most of elements and constitution of a conventional memory device 200 illustrated in FIG. 3 are similar except that the decoupling capacitor 104 is directly connected to the buried contact 130b because the buffer layer 131b is omitted in the peripheral circuit region B. Because like reference numerals in FIG. 3 denote like elements in FIG. 1, further descriptions of the elements of conventional memory device 200 will be omitted.
In FIG. 3, the buried contact 130b is used as a connection line for serially connecting the plurality of decoupling capacitors 104 in the peripheral circuit region B of the conventional memory device 200.
However, by using the buried contact 130b as the connection line for connecting the decoupling capacitors 104 in series, there may be a decrease in the capacitance of the decoupling capacitor 104 due to high resistance of the buried contact 130b. 
While it still may be possible to implement the decoupling capacitor of a two stage cell type in which two capacitors are connected to each other in series as illustrated in FIG. 2, there is still a drawback in that it is difficult to implement the decoupling capacitor of a single stage cell type in which only one capacitor is represented in an equivalent circuit. The reason is that at the present time, it is impossible to form the interconnection for directly connecting the buried contact 130b to the metal interconnection 140 due to limitations in the manufacturing process.